Automatic circuit analysis based on mask information
DAC '76 Proceedings of the 13th Design Automation Conference
An artwork design verification system
DAC '75 Proceedings of the 12th Design Automation Conference
Circuit simulation and timing verification based on MOS/LSI mask information
DAC '79 Proceedings of the 16th Design Automation Conference
Topological analysis for VLSI circuits
DAC '79 Proceedings of the 16th Design Automation Conference
Hcompare: a hierarchical netlist comparison program
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Hierarchical circuit verification
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Symbolic Parasitic Extractor for Circuit Simulation (SPECS)
DAC '83 Proceedings of the 20th Design Automation Conference
Programs for verifying circuit connectivity of mos/lsi mask artwork
DAC '82 Proceedings of the 19th Design Automation Conference
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This paper describes a CAD program which checks the circuit topology and the electrical parameters from the IC layout data against the user supplied circuit descriptions. Taking advantage of the hierarchical characteristics of the layout data, the program achieves an efficient analysis and does a clear presentation of the results.