DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
An O (N log N) algorithm for Boolean mask operations
DAC '81 Proceedings of the 18th Design Automation Conference
Technology independent arbitrary device extractor
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
An efficient algorithm for partitioning parameterized polygons into rectangles
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Partitioning parameterized 45-degree polygons with constraint programming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A parallel dual-scanline algorithm for partitioning parameterized 45-degree polygons
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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In non-Manhattan geometry layout extraction, polygon to trapezoid decomposition is an indispensable step. Its efficiency and the organization of generated trapezoids significantly affect the performance of layout extractors. We present a new polygon to trapezoid decomposition algorithm used in our layout extractor iLEX. The concept of edge pair and scanline interval are introduced to provide improved efficiency over conventional scanline algorithms. Definitions for trapezoid corner stitches are provided as well as integrated algorithms on corner stitching trapezoids generated. Complexity analysis shows that our scanline algorithm has an expected computation time of &Ogr;(n log n), and an expected space of &Ogr;(√n), where n is the number of non-vertical edges in the given layout.