Layout design and verification
Layout design and verification
An intelligent design system for analogue integrated circuits
EURO-DAC '90 Proceedings of the conference on European design automation
A new approach to layout of custom analog cells
EURO-DAC '91 Proceedings of the conference on European design automation
Algorithms for automatic length compensation of busses in analog integrated circuits
Proceedings of the 2007 international symposium on Physical design
A parallel dual-scanline algorithm for partitioning parameterized 45-degree polygons
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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We present an interactive two layer router integrated in an analog IC design environment used in an SDL (schematic driven layout) design flow. Special features are its customizability, the treatment of arbitrary polygons and an advanced handling of source/target polygons in order to avoid net internal design rule violations during connection phase A global routing algorithm is used to split the route into separate parts each routable in a single layer. After via placement a specialized maze router performs the advanced single layer routes in 90 or 45 degree mode. The resulting route can be modified by interactive via movement and rerouting of obsolete partial routes.