Layout-oriented synthesis of high performance analog circuits
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A layout-aware synthesis methodology for RF circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Accurate Estimation of Parasitic Capacitances in Analog Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Extraction and use of neural network models in automated synthesis of operational amplifiers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance space modeling for hierarchical synthesis of analog integrated circuits
Proceedings of the 42nd annual Design Automation Conference
Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
An efficient algorithm for partitioning parameterized polygons into rectangles
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Partitioning parameterized 45-degree polygons with constraint programming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Template coding with LDS and applications of LDS in EDA
Analog Integrated Circuits and Signal Processing
| Hi-index | 0.00 |
Considering layout effects early in the analog design process is becoming increasingly important. We propose techniques for estimating parasitic capacitances based on look-up tables and multi-variate linear interpolation. These models enable fast and accurate estimation of parasitic capacitances and are very suitable for use in a synthesis flow. A layout aware methodology for synthesis of analog CMOS circuits using these parasitic models is presented. Results indicate that the proposed synthesis system is fast as compared to a layout-inclusive synthesis approach.