Optimization of Wafer Scale H-Tree Clock Distribution Network Based on a New Statistical Skew Model

Authors:
Xiaohong Jiang;Susumu Horiguchi
Affiliations:
-;-
Venue:
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Year:
2000

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Abstract

Available statistical skew model is too conservative to estimate the expected clock skew of a well-balanced H-tree. New closed form model is presented for accurately estimating the expected values and the variances of both clock skew and the largest clock delay of a well-balanced H-tree. Based on the new model, clock period optimization of wafer scale H-tree clock network is investigated under two clocking modes. We find that when the conventional clocking mode is used, clock period optimization of wafer scale H-tree is reduced to the minimization of expected largest clock delay under both area restriction and power restriction. On the other hand, when the pipelined clocking mode is considered, the optimization is reduced to the minimization of expected clock skew under power restriction.