PLDI '92 Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation
Sentinel scheduling: a model for compiler-controlled speculative execution
ACM Transactions on Computer Systems (TOCS)
Complete removal of redundant expressions
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
Register promotion by sparse partial redundancy elimination of loads and stores
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
Integrated predicated and speculative execution in the IMPACT EPIC architecture
Proceedings of the 25th annual international symposium on Computer architecture
Efficient and precise modeling of exceptions for the analysis of Java programs
Proceedings of the 1999 ACM SIGPLAN-SIGSOFT workshop on Program analysis for software tools and engineering
Partial redundancy elimination in SSA form
ACM Transactions on Programming Languages and Systems (TOPLAS)
ABCD: eliminating array bounds checks on demand
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Global optimization by suppression of partial redundancies
Communications of the ACM
Exploring the Interaction between Java's Implicitly Thrown Exceptions and Instruction Scheduling
International Journal of Parallel Programming
The Java Language Specification
The Java Language Specification
Effective Representation of Aliases and Indirect Memory Operations in SSA Form
CC '96 Proceedings of the 6th International Conference on Compiler Construction
An efficient static analysis algorithm to detect redundant memory operations
Proceedings of the 2002 workshop on Memory system performance
Optimal and efficient speculation-based partial redundancy elimination
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Optimizing for space and time usage with speculative partial redundancy elimination
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Partial redundancy elimination for access expressions by speculative code motion
Software—Practice & Experience
A verifiable SSA program representation for aggressive compiler optimization
Conference record of the 33rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
A lifetime optimal algorithm for speculative PRE
ACM Transactions on Architecture and Code Optimization (TACO)
Trace Scheduling: A Technique for Global Microcode Compaction
IEEE Transactions on Computers
An SSA-based algorithm for optimal speculative code motion under an execution profile
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
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Compilers for Java and other type-safe languages have historically worked to overcome overheads and constraints imposed by runtime safety checks and precise exception semantics. We instead exploit these safety properties to perform code motion optimizations that are even more aggressive than those possible in unsafe languages such as C++. We present a novel framework for speculative motion of dangerous (potentially faulting) instructions in safe, object-oriented languages such as Java and C#. Unlike earlier work, our approach requires no hardware or operating system support. We leverage the properties already provided by a safe language to define fault safety, a more precise notion of safety that guarantees that a dangerous operation (e.g., a memory load) will not fault at a given program point. We illustrate how typical code motion optimizations are easily adapted to exploit our safety framework. First, we modify the standard SSAPRE partial redundancy elimination (PRE) algorithm to use fault safety, rather than the traditional down safety property. Our modified algorithm better exploits profile information by inserting of dangerous instructions on new paths when it is profitable and provably safe. Second, we extend an instruction trace scheduler to use fault safety to safely schedule load instructions across branches to better tolerate memory latency and to more compactly target instruction slots. We implemented these optimizations in StarJIT, a dynamic compiler, and show performance benefits of up to 10% on a set of standard Java benchmarks.