Multiprocessor mapping of process networks: a JPEG decoding case study
Proceedings of the 15th international symposium on System Synthesis
Algorithmic transformation techniques for efficient exploration of alternative application instances
Proceedings of the tenth international symposium on Hardware/software codesign
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Optimized Generation of Data-Path from C Codes for FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
pn: a tool for improved derivation of process networks
EURASIP Journal on Embedded Systems
Systematic and Automated Multiprocessor System Design, Programming, and Implementation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design and implementation of an operating system for composable processor sharing
Microprocessors & Microsystems
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The demand for embedded computing power is continuously increasing and FPGAs are becoming very interesting computing platforms, as they provide huge amounts of customizable parallelism. However, programming them is challenging, let alone from a high level language. In [1], the Espam methodology was already presented to quickly obtain realizations on FPGAs from sequential C code. The realization consists of a network of processors and IP cores. In this approach, a problem was that the IP cores had to be provided manually. In this paper, we present an extension on the Espam methodology by incorporating the industrial high level synthesis tool Pico from Synfora Inc. In this way, we realize the automated generation of efficient hardware implementations on FPGAs from a single sequential C input specification of a streaming application. We demonstrate our approach for the Sobel and QR applications.