Applying frame layout to hardware design in FPGA for seamless support of cross calls in CPU-FPGA coupling architecture

Authors:
Giang Nguyen Thi Huong;Yeoul Na;Seon Wook Kim
Affiliations:
Compiler and Microarchitecture Laboratory, School of Electrical Engineering, Korea University, Seoul 136-701, Republic of Korea;Compiler and Microarchitecture Laboratory, School of Electrical Engineering, Korea University, Seoul 136-701, Republic of Korea;Compiler and Microarchitecture Laboratory, School of Electrical Engineering, Korea University, Seoul 136-701, Republic of Korea
Venue:
Microprocessors & Microsystems
Year:
2011

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Abstract

A cross call between a host processor and FPGA is one of the main challenges for supporting automatic translation of high-level languages into hardware description languages (HDL). In this paper, we present a novel communication framework between the processor and FPGA, which supports unlimited cross calls and hardware recursive calls by following the software's frame layout in HDL code generation and sharing a stack space between software and hardware codes. Also, we introduce two implementation methods for our cross call, a direct and an indirect interfaces by an instruction-level and an interrupt communication, respectively. Our experiment shows that the proposed approach achieves our goal with small additional complexity in implementation and insignificant overhead in execution time.