Heuristic tradeoffs between latency and energy consumption in register assignment

Authors:
R. Anand;M. Jacome;G. de Veciana
Affiliations:
Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX;Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX;Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX
Venue:
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Year:
2000

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Abstract

One of the challenging tasks in code generation for embedded systems is register allocation and assignment, wherein one decides on the placement and lifetimes of variables in registers. When there are more live variables than registers, some variables need to be spilled to memory and restored later. In this paper we propose a policy that minimizes the number of spills — which is critical for portable embedded systems since it leads to a decrease in energy consumption. We argue however, that schedules with a minimal number of spills do not necessarily have minimum latency. Accordingly, we propose a class of policies that explore tradeoffs between assignments leading to schedules with low latency versus those leading to low energy consumption and show how to tune them to particular datapath characteristics. Based on experimental results we propose a criterion to select a register assignment policy that for 99% of the cases we considered minimizes both latency and energy consumption associated with spills to memory.