Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Optimization
Optimal VLSI architectural synthesis: area, performance and testability
Optimal VLSI architectural synthesis: area, performance and testability
The Journal of Supercomputing - Special issue on instruction-level parallelism
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Optimal instruction scheduling using integer programming
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Retargetable Code Generation for Digital Signal Processors
Retargetable Code Generation for Digital Signal Processors
Code Generation for Embedded Processors
Code Generation for Embedded Processors
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Scheduling expression trees for delayed-load architectures
Journal of Systems Architecture: the EUROMICRO Journal
Just-In-Time Java? Compilation for the Itanium® Processor
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Optimizing Compiler for the CELL Processor
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Reducing code size in VLIW instruction scheduling
Journal of Embedded Computing - Low-power Embedded Systems
Application driven embedded system design: a face recognition case study
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
An Application of Constraint Programming to Superblock Instruction Scheduling
CP '08 Proceedings of the 14th international conference on Principles and Practice of Constraint Programming
ILP optimal scheduling for multi-module memory
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Variable assignment and instruction scheduling for processor with multi-module memory
Microprocessors & Microsystems
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The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply/accumulate units and SIMD operations for 3D graphics operations. In this paper we present an ILP formulation for the problem of instruction scheduling for IA-64. In order to obtain a feasible schedule it is necessary to model the data dependences, resource constraints as well as additional encoding restrictions—the bundling mechanism. These different aspects represent subproblems that are closely coupled which gives the motivation for a modeling based on integer linear programming. The presented approach is divided in to two phases which allows us to compute mostly optimal solutions with acceptable computation time.