Bit-level optimization for high-level synthesis and FPGA-based acceleration

Authors:
Jiyu Zhang;Zhiru Zhang;Sheng Zhou;Mingxing Tan;Xianhua Liu;Xu Cheng;Jason Cong
Affiliations:
Peking University, Beijing, China;AutoESL Design Technologies, Los Angeles, CA, USA;AutoESL Design Technologies, Los Angeles, CA, USA;Peking University, Beijing, China;Peking University, Beijing, China;Peking University, Beijing, China;University Of California, Los Angeles/ UCLA-PKU Joint Research Institute in Science and Engineering, Los Angeles, CA, USA
Venue:
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Year:
2010

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Abstract

Automated hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level programming languages, such as C/C++, the description of bitwise access and computation is not as direct as hardware description languages, and high-level synthesis of algorithmic descriptions may generate suboptimal implementations for bitwise computation-intensive applications. In this paper we introduce a bit-level transformation and optimization approach to assisting high-level synthesis of algorithmic descriptions. We introduce a bit-flow graph to capture bit-value information. Analysis and optimizing transformations can be performed on this representation, and the optimized results are transformed back to the standard data-flow graphs extended with a few instructions representing bitwise access. This allows high-level synthesis tools to automatically generate circuits with higher quality. Experiments show that our algorithm can reduce slice usage by 29.8% on average for a set of real-life benchmarks on Xilinx Virtex-4 FPGAs. In the meantime, the clock period is reduced by 13.6% on average, with an 11.4% latency reduction.