Optimization of a logic circuit implementing a Moore automaton in CPLD basis

  • Authors:

  • A. A. Barkalov;L. A. Titarenko;S. A. Tsololo

  • Affiliations:

  • Donetsk National Technical University, Donetsk, Ukraine;Kharkov University of Radio Electronics, Kharkov, Ukraine;Donetsk National Technical University, Donetsk, Ukraine

  • Venue:
  • Cybernetics and Systems Analysis
  • Year:
  • 2009

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Abstract

A method is proposed for optimization of hardware expenditures for the implementation of Moore automatons (Moore FSMs) in CPLDs. The method lies in using several sources of codes of classes of pseudo-equivalent states, which is possible owing to a wide fan-in of PAL macrocells. The proposed method generates five new circuit models of a Moore automaton. A method of synthesis of a model with three sources of codes is proposed, and an example of its application is presented.