Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
The Design Warrior's Guide to FPGAs
The Design Warrior's Guide to FPGAs
FSM-based Digital Design using Verilog HDL
FSM-based Digital Design using Verilog HDL
Logic Synthesis for Compositional Microprogram Control Units
Logic Synthesis for Compositional Microprogram Control Units
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Two methods are proposed for microinstruction addressing in interpreting a control algorithm by a compositional microprogram control unit (CMCU). The method of refined addressing allows one to uniquely identify outputs of operational linear chains (OLCs) using a minimal number of address bits. The method of optimal addressing makes it possible to represent classes of pseudoequivalent OLCs using a minimal number of generalized intervals of the code space. The proposed methods are illustrated by examples. Both methods make it possible to reduce the number of look-up table (LUT) elements in a CMCU logic circuit in comparison with its base structure. In the majority of cases, the clock period decreases with decreasing the amount of hardware