Application of Reconfigurable CORDIC Architectures

Authors:
Oskar Mencer;Luc Séméria;Martin Morf;Jean-Marc Delosme
Affiliations:
Computer Systems Laboratory, Department of Electrical Engineering, Stanford, CA 94305, USA;Computer Systems Laboratory, Department of Electrical Engineering, Stanford, CA 94305, USA;Computer Systems Laboratory, Department of Electrical Engineering, Stanford, CA 94305, USA;Département Informatique, Université d'Evry, Cours Monseigneur Romero, 91025 Evry, France
Venue:
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Year:
2000

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Abstract

Reconfiguration enables the adaption of Coordinate RotationDIgital Computer (CORDIC) units to the specific needs of sets ofapplications, hence creating application specific CORDIC-styleimplementations. Reconfiguration can be implemented at a high level,taking the entire CORDIC unit as a basic cell (CORDIC-cells)implemented in VLSI, or at a low level such as Field-ProgrammableGate Arrays (FPGAs). We suggest a design methodology and analyzearea/time results for coarse (VLSI) and fine-grain (FPGA)reconfigurable CORDIC units. For FPGAs we implement CORDIC units inVerilog HDL and our object-oriented design environment, PAM-Blox. ForCORDIC-cells, multiple reconfigurable CORDIC modules are synthesizedwith state-of-the-art CAD tools. At the algorithm level we present acase study combining multiple CORDICs based on a geometricalinterpretation of a normalized ladder algorithm for adaptivefiltering to reduce latency and area of a fully pipelined CORDICimplementation. Ultimately, the goal is to create automatic tools tomap applications directly to reconfigurable high-level arithmeticunits such as CORDICs.