Elementary functions: algorithms and implementation
Elementary functions: algorithms and implementation
A survey of CORDIC algorithms for FPGA based computers
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
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MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Approximating Elementary Functions with Symmetric Bipartite Tables
IEEE Transactions on Computers
Application of Reconfigurable CORDIC Architectures
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers
IEEE Transactions on Computers
StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
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FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
PAM-Blox: High Performance FPGA Design for Adaptive Computing
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
PCI-PipeRench and the SWORDAPI: A System for Stream-Based Reconfigurable Computing
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Signal processing algorithms and architectures
Signal processing algorithms and architectures
Rational arithmetic units in computer systems
Rational arithmetic units in computer systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-Performance Quasi-Monte Carlo Financial Simulation: FPGA vs. GPP vs. GPU
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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This paper presents parameterized module-generators for pipelined function evaluation using lookup tables, adders, shifters and multipliers. We discuss trade-offs involved between (1) full-lookup tables, (2) bipartite (lookup-add) units, (3) lookup-multiply units, and (4) shift-and-add based CORDIC units. For lookup-multiply units we provide equations estimating approximation errors and rounding errors which are used to parameterize the hardware units. The resources and performance of the resulting design can be estimated given the input parameters. The method is implemented as part of the PAM-Blox module generation environment. An example shows that the lookup-multiply unit produces competitive designs with data widths up to 20 bits when compared with shift-and-add based CORDIC units. Additionally, the lookup-multiply method can be used for larger data widths when evaluating functions not supported by CORDIC.