A dynamic network architecture
ACM Transactions on Computer Systems (TOCS)
ACM Transactions on Computer Systems (TOCS)
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Mapping a domain specific language to a platform FPGA
Proceedings of the 41st annual Design Automation Conference
Hyper-Programmable Architectures for Adaptable Networked Systems
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
CUSP: a modular framework for high speed network applications on FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Gigabit Ethernet switches using a shared buffer architecture
IEEE Communications Magazine
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Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the features of the system. We propose a high-level synthesis technique for a new model for representing packet editing functions. Experiments show our circuits achieve a throughput of up to 40Gb/s on a commercially available FPGA device, equal to state-of-the-art implementations.