A novel parallel deadlock detection algorithm and architecture

Authors:
Pun H. Shiu;YuDong Tan;Vincent J. Mooney, III
Affiliations:
Electrical and Computer Engineering, Georgia Institute of Technology;Electrical and Computer Engineering, Georgia Institute of Technology;Electrical and Computer Engineering, Georgia Institute of Technology
Venue:
Proceedings of the ninth international symposium on Hardware/software codesign
Year:
2001

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Abstract

A novel deadlock detection algorithm and its hardware implementation are presented in this paper. The hardware deadlock detection algorithm has a run time complexity of &Ogr;hw (min(m,n)), where m and n are the number of processors and resources, respectively. Previous algorithms based on a Resource Allocation Graph have &Ogr;sw (m × n) run time complexity for the worst case. We simulate a realistic example in which the hardware deadlock detection unit is applied, and demonstrate that the hardware implementation of the novel deadlock detection algorithm reduces deadlock detection time by 99.5%. Furthermore, in a realistic example, total execution time is reduced by 68.9%.