Operation systems: advanced concepts
Operation systems: advanced concepts
A new viewpoint on two-level logic minimization
DAC '93 Proceedings of the 30th international Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
IEEE Spectrum
ACM Computing Surveys (CSUR)
Some Deadlock Properties of Computer Systems
ACM Computing Surveys (CSUR)
A novel parallel deadlock detection algorithm and architecture
Proceedings of the ninth international symposium on Hardware/software codesign
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
A deadlock detection and recovery algorithm using the formalism of a directed graph matrix
ACM SIGOPS Operating Systems Review
Hardware/software deadlock avoidance for multiprocessor multiresource system-on-a-chip
Hardware/software deadlock avoidance for multiprocessor multiresource system-on-a-chip
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This article presents a novel Parallel Deadlock Detection Algorithm (PDDA) and its hardware implementation, Deadlock Detection Unit (DDU). PDDA uses simple Boolean representations of request, grant, and no activity so that the hardware implementation of PDDA becomes easier and operates faster. We prove the correctness of PDDA and that the DDU has a runtime complexity of O(min(m,n)), where m is the number of resources and n is the number of processes. The DDU reduces deadlock detection time by 99%, (i.e., 100X) or more compared to software implementations of deadlock detection algorithms. An experiment involving a practical situation with an early deadlock condition showed that the time measured from application initialization to deadlock detection was reduced by 46% by employing the DDU as compared to detecting deadlock in software.