Formal Pipeline Design

  • Authors:
  • Tiberiu Seceleanu;Juha Plosila

  • Affiliations:
  • -;-

  • Venue:
  • CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
  • Year:
  • 2001

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Abstract

The action systems formalism has recently been applied to the area of asynchronous and synchronous VLSI design. In this paper, we study formal aspects of synchronous pipelining. We show how the framework of synchronous action systems can be used to derive a pipelined structure from a non-pipelined specification in a correctness-preserving manner.