Two-level logic minimization: an overview
Integration, the VLSI Journal
Worst and Best Irredundant Sum-of-Products Expressions
IEEE Transactions on Computers
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Large-scale SOP minimization using decomposition and functional properties
Proceedings of the 40th annual Design Automation Conference
Algorithms
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In this study we propose a new method for iteratively covering given Boolean data set by its prime implicants identified one at a time. In contrast to existing set covering methods of NP time complexity in the size of the set, our method is realized by procedures of linear complexity and therefore its efficiency is rapidly increased by increasing the size of the set. Our method can be useful in all fields related to Boolean data sets processing such as logic synthesis, image processing, data compressing, artificial intelligence and many others.