Evolutionary algorithms for VLSI CAD
Evolutionary algorithms for VLSI CAD
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Test vector decomposition-based static compaction algorithms for combinational circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
MapReduce: simplified data processing on large clusters
Communications of the ACM - 50th anniversary issue: 1958 - 2008
Comparative Study by Solving the Test Compaction Problem
ISMVL '08 Proceedings of the 38th International Symposium on Multiple Valued Logic
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A parallel evolutionary approach of Compaction Problem is introduced usingMapReduce. This problem is of interest for VLSI testing and bioinformatics. The overall cost of a VLSI circuit's testing depends on the length of its test sequence; therefore the reduction of this sequence, keeping the coverage, will lead to a reduction of used resources in the testing process. The problem of finding minimal test sets is NP-hard. We introduce a distributed evolutionary algorithm (MapReduce Parallel Evolutionary Algorithm-MRPEA) and compare it with two greedy approaches. The proposed algorithms are evaluated on randomly generated five-valued benchmarks that are scalable in size. The MapReduce paradigm offers the possibility to distribute and scale large amount of data. Experiments show the efficiency of the proposed parallel approach. The project, containing the Hadoop implementation can be found at: http://sourceforge.net/projects/dcpsolver/ [10].