ISSS '00 Proceedings of the 13th international symposium on System synthesis
A global approach to improve conditional hardware reuse in high-level synthesis
Journal of Systems Architecture: the EUROMICRO Journal
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
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Conditional resource sharing has been identified as a possibility for optimizing high-level synthesis results. In this paper we propose a Hierarchical Conditional Dependency Graph representation that permits to treat conditional resource sharing in a generic fashion depending on the specific context, i.e. functional units, storage elements and interconnects. Resource usage conditions are represented in a control hierarchy of BDD trees that permits toefficiently reason on condition exclusiveness. These ideas are illustrated by a scheduling example.