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The next generation of computer chips will continue the trend for more complexity than their predecessors. Many of them will contain different chip technologies and are termed SoCs (System on a Chip). They present to the process community, the system and circuit communities, as well as to the design and test communities major new challenges. On the other hand they also offer at the same time also new opportunities!. For one, the desire to bring more functionality onto a single chip tends to require additional processing, which in turn results in various degrees of device compromises. The chips will also tend to become larger due to the added device content, and this generally will impact the yieldability of the final chip. And such chips will require potentially new approaches to validate the intended design performances. Chip sector reuse must also be brought into the discussion and wherever possible into practice. The net effect implies higher chip costs. Much of the industry's efforts are therefore focused in addressing these challenges; however, so far, not yet very successfully. The alternative has been to continue in the placement of chips onto substrate modules. Yet, this solution creates practical limits on achievable wiring densities and bandwidth, due to the spacing requirements of the C4 interconnection. Furthermore, every C4 joint is associated with a signal delay of about 50 psec. All of these handicaps would potentially benefit greatly from new SoC methods, starting with the fabrication methodology and extending it into the chip design and test areas.Such a direction has been set in motion. The opportunity for a uniquely new chip fabrication method has emerged by combining a set of somewhat diverse processes. It is based on a judicious selection of process elements from the traditional chip area and combined with those of a somewhat more recent chip packaging process methodology. This approach results in overcoming simultaneously all of the key current process limitations as experienced with today's SoC chip designs, as well as eliminates certain chip packaging technology handicaps. Yet, it does not require the need for new process tooling. It relies on currently existing process tooling and process methodologies.New opportunities for yet another expansion of theThis new process direction has been found to be quite applicable to a number of desirable SoC device designs, and offers current semiconductor technology base over the next few years. However, effective SoC designs and fabrications require a much closer and earlier collaboration between the process, design and test communities.