Design of Reconfigurable Access Wrappers for Embedded Core Based SOC Test

• Venue: ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
• Year: 2002

Testing of embedded core based system-on-chip (SOC) ICs is a well known problem, and the upcoming IEEE P1500 (SECT) standard proposes DfT solutions to alleviate it. One of the proposals is to provide every core in the SOC with test access wrappers. Previous approaches to the problem of wrapper design have proposed static core wrappers, which are designed for a particular test access mechanism (TAM) width. We present the first report of a design of reconfigurable core wrappers. An automatic procedure for the creation of DfT required for reconfiguration using a graph theoretic representation of core wrappers is also presented. Our method is superior to previously published methods as it admits dynamic reconfiguration of core level scan access structures with little area and delay over-head. Using reconfigurable core wrappers the quality of the SOC test schedule can be improved. Theoretical analysis of the corresponding scheduling problem indicates that good approximate schedules can be achieved without significant computational effort. Experimental results demonstrate that our method outperforms state-of-art ILP formulations by as much as 15%.