Opens and Delay Faults in CMOS RAM Address Decoders

Authors:
Said Hamdioui;Zaid Al-Ars;Ad J. van de Goor
Affiliations:
-;-;-
Venue:
IEEE Transactions on Computers
Year:
2006

Citing 6
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Abstract

This paper presents a complete electrical analysis of Address decoder Delay Faults "ADFs” caused by resistive opens in RAMs. A classification between inter and intragate opens is made. A systematic way is introduced to explore the space of possible tests to detect these faults; it is based on generating appropriate sensitizing address transitions and the corresponding sensitizing operation sequences. DFT features are given to facilitate the BIST implementation of the new tests.