A distributed architecture model for heterogeneous multiprocessor system-on-chip design

Authors:
Qiang Wu;Jinian Bian;Hongxi Xue
Affiliations:
,Department of Computer Science and Technology, Tsinghua University, Beijing, China;Department of Computer Science and Technology, Tsinghua University, Beijing, China;Department of Computer Science and Technology, Tsinghua University, Beijing, China
Venue:
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
Year:
2004

Citing 11
Cited 0

An efficient architecture model for systematic design of application-specific multiprocessor SoC

Proceedings of the conference on Design, automation and test in Europe
Component-based design approach for multicore SoCs

Proceedings of the 39th annual Design Automation Conference
System-on-a-Chip: Design and Test

System-on-a-Chip: Design and Test
Hardware/Software CO-Design: Principles and Practice

Hardware/Software CO-Design: Principles and Practice
Platform-Based Design and Software Design Methodology for Embedded Systems

IEEE Design & Test
Top-Down System Level Design Methodology Using SpecC, VCC and SystemC

Proceedings of the conference on Design, automation and test in Europe
Multiprocessor Architectures for Embedded System-on-chip Applications

VLSID '04 Proceedings of the 17th International Conference on VLSI Design
High-Throughput Programmable Cryptocoprocessor

IEEE Micro
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Guest Editors' Introduction: Hot Chips 15--Scaling the Silicon Mountain

IEEE Micro
Anatomy of a Portable Digital Mediaprocessor

IEEE Micro

Quantified Score

Hi-index	0.00

Visualization

Abstract

Current embedded system designs inspire the adoption of heterogeneous multiprocessor system-on-chip (SoC) technology, in which the architecture model plays a very important role. This paper proposes a distributed architecture model for the heterogeneous multiprocessor SoC design. It takes the view on the system as multiple processing elements connected with a network of communication channels. System functions are refined to primitives provided by the processing elements and communication channels through a hierarchy of abstraction layers. This will be helpful for the enhancement of system design modularity and efficiency.