HIBRID-SOC: a multi-core architecture for image and video applications

  • Authors:

  • S. Moch;M. Bereković;H. J. Stolberg;L. Friebe;M. B. Kulaczewski;A. Dehnhardt;P. Pirsch

  • Affiliations:

  • Universität Hannover, Germany;Universität Hannover, Germany;Universität Hannover, Germany;Universität Hannover, Germany;Universität Hannover, Germany;Universität Hannover, Germany;Universität Hannover, Germany

  • Venue:
  • MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
  • Year:
  • 2003

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Abstract

The HiBRID-SoC multi-core architecture targets a wide range of application fields with particularly high processing demands, including general signal processing applications, video de-encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processor cores and various interfaces on a single chip, all tied to a 64-Bit AMBA AHB bus. Its memory subsystem is particularly adapted to the high bandwidth demands of the multi-core architecture by providing several DMA capabilities and multiple data transfer paths. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system costs. The HiBRID-SoC is fabricated in a 0.18 μm 6LM standard-cell technology, occupies about 82 mm2, operates at 145 MHz, and comsumes 3.5 Watts.