Discrete-time signal processing
Discrete-time signal processing
Architectures for Digital Signal Processing
Architectures for Digital Signal Processing
Programmable implementations of xDSL transceiver systems
IEEE Communications Magazine
HIBRID-SOC: a multi-core architecture for image and video applications
MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
Bit manipulation accelerator for communication systems digital signal processor
EURASIP Journal on Applied Signal Processing
BrickX: building hybrid systems for recursive computations
ACM SIGMETRICS Performance Evaluation Review
A low-power globally synchronous locally asynchronous FFT processor
HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
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This paper presents new DSP (Digital Signal Processor) instructions and their hardware architecture for high-speed FFT. The instructions perform new operation flows, which are different from the MAC (Multiply and Accumulate) operation on which existing DSP chips heavily depend. This paper proposes the DPU (Data Processing Unit) supporting the instructions and shows it to be two times faster than existing DSP chips for FFT. The architecture has been modeled by the Verilog HDL and logic synthesis has been performed using the 0.35 μm standard cell library. The maximum operating clock frequency is about 144.5 MHz and the architecture will be employed on an application-specific DSP chip.