One-Step Compilation of Image Processing Applications to FPGAs

Authors:
A. P. W. Bohm;B. Draper;W. Najjar;J. Hammes;R. Rinker;M. Chawathe;C. Ross
Affiliations:
Colorado State University;Colorado State University;Colorado State University;Colorado State University;Colorado State University;Colorado State University;Colorado State University
Venue:
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
2001

Citing 0
Cited 5

High-Level Language Abstraction for Reconfigurable Computing

Computer
ARCHITECT-R: a system for reconfigurable robots design

Proceedings of the 2003 ACM symposium on Applied computing
Compile-time area estimation for LUT-based FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Compiling for reconfigurable computing: A survey

ACM Computing Surveys (CSUR)
Domain-Specific Optimization of Signal Recognition Targeting FPGAs

ACM Transactions on Reconfigurable Technology and Systems (TRETS)

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper describes a system for one-step compilation of image processing (IP) codes, written in the machine-independent, algorithmic, high-level single assignment language SA-C, to FPGA-based hardware. The SA - C compiler performs a variety of optimizations, some conventional and some specialized, before generating dataflow graphs and host code. The dataflow graphs are then compiled, via VHDL, to FPGA configuration codes. This paper introduces SA - C and describes the optimization and code generation stages in the compiler. The performance of a target acquisition prescreener (ARAGTAP), the Intel Image Processing Library, and an iterative tri-diagonal solver running on a reconfigurable system are compared to their performance on a Ppentium PC with MMX.