A new statistical model for gate array routing

  • Authors:

  • Abbas El Gamal;Zahir A. Syed

  • Affiliations:

  • 137 Durand Building, Information Systems Lab., Stanford University, Stanford, CA;137 Durand Building, Information Systems Lab., Stanford University, Stanford, CA

  • Venue:
  • DAC '83 Proceedings of the 20th Design Automation Conference
  • Year:
  • 1983

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Abstract

A new statistical model for routing of gate arrays is described. The model takes into consideration the effect of gate utilization on wiring area requirement. Model computed wiring area estimates suggest that it is better (in terms of area and wire length) to use higher utilization and a relatively large number of tracks than low utilization and smaller number of tracks. This is shown to be consistent with the results of two experiments.