On routing for custom integrated circuits
DAC '82 Proceedings of the 19th Design Automation Conference
A complexity theory for VLSI
Automated data-memory synthesis: a formal method for the specification, analysis, and design of register-transfer level digital logic
Integrated scheduling and binding: a synthesis approach for design space exploration
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The effects of physical design characteristics on the area-performance tradeoff curve
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
PLEST: a program for area estimation of VLSI integrated circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
| Hi-index | 0.00 |
This paper describes an experiment to determine how register-transfer tradeoffs affect the resultant silicon area and performance of layouts. Six register-transfer level designs, each performing the same function with different register transfer level structures, were implemented using a library of CMOS/SOS standard cells, and an automatic placement and routing program. The consumption of area and the critical path timing were calculated for each design. The results show that register-transfer design variations do produce changes in area and performance at the layout level. However, optimistic timing analysis at the RT level, variations in relative storage timing across technologies, and omission of fanout and path length delays altered the resultant area and timing from that predicted at the RT level.