A new circuit placement program for FET chips

  • Authors:
  • K. W. Lallier;R. K. Jackson

  • Affiliations:
  • -;-

  • Venue:
  • DAC '79 Proceedings of the 16th Design Automation Conference
  • Year:
  • 1979

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Abstract

A new solution to the problem of automated placement of FET circuits has been implemented. This new approach automatically realizes a global solution to the problem yielding circuit location, circuit orientation, all cross column wires and blanks between circuits, thus eliminating many of the most tedious and error prone steps in physical design. The technique is based upon “natural selection” and obtains a solution using a series of sweeps through the columns evolving circuit position and cross column wiring assignments together. Scoring is done to minimize column peaks.