Optimal cascade lumped model of deep submicron on-chip interconnect with distributed parameters

Authors:
Ma Qungang;Yang Yintang;Li Yuejin;Jia Xinzhang
Affiliations:
Institute of Microelectronics, Graduate School of Xidian University, Southern Taibai Road No. 2, 710071 Xi'an, Shaanxi, PR China;Institute of Microelectronics, Graduate School of Xidian University, Southern Taibai Road No. 2, 710071 Xi'an, Shaanxi, PR China;Institute of Microelectronics, Graduate School of Xidian University, Southern Taibai Road No. 2, 710071 Xi'an, Shaanxi, PR China;Institute of Microelectronics, Graduate School of Xidian University, Southern Taibai Road No. 2, 710071 Xi'an, Shaanxi, PR China
Venue:
Microelectronic Engineering
Year:
2005

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Abstract

A rapidly responding yet highly accurate on-chip interconnect simulation model, an optimal cascade lumped model, is presented. Compared with previous interconnect simulating models with similar parameters, the new model expends less CPU time and provides simple closed-form expressions for accurate number of repeated RLCG or LC models, which are proved by the simulation results of 0.18, 0.13, 0.07 and 0.05 @mm. It is valuable to guide the analysis and the simulation of deep submicron VLSI circuits with billions of interconnects.