Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Wire shaping of RLC interconnects
Integration, the VLSI Journal
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We present an algorithm for delay minimization of interconnect trees by simultaneous buffer insertion/sizing and wire sizing in this paper. Both wire widths and buffer sizes are chosen from user-defined discrete sets. Our algorithm integrates the quadratic programming approach for handling a wire branch into the dynamic programming (DP) framework. Our experimental results show that our hybrid dynamic/quadratic programming algorithm is faster, more accurate, and uses considerably less memory than the pure DP approach