Secure History Preservation Through Timeline Entanglement
Proceedings of the 11th USENIX Security Symposium
Historic integrity in distributed systems
Historic integrity in distributed systems
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
Pioneer: verifying code integrity and enforcing untampered code execution on legacy systems
Proceedings of the twentieth ACM symposium on Operating systems principles
Measuring the gap between FPGAs and ASICs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Externally verifiable code execution
Communications of the ACM - Privacy and security in highly dynamic systems
Prerendered user interfaces for higher-assurance electronic voting
EVT'06 Proceedings of the USENIX/Accurate Electronic Voting Technology Workshop 2006 on Electronic Voting Technology Workshop
IEEE Security and Privacy
Designing voting machines for verification
USENIX-SS'06 Proceedings of the 15th conference on USENIX Security Symposium - Volume 15
Reconfigurable trusted computing in hardware
Proceedings of the 2007 ACM workshop on Scalable trusted computing
Casting votes in the auditorium
EVT'07 Proceedings of the USENIX Workshop on Accurate Electronic Voting Technology
Extending prerendered-interface voting software to support accessibility and other ballot features
EVT'07 Proceedings of the USENIX Workshop on Accurate Electronic Voting Technology
On the difficulty of validating voting machine software with software
EVT'07 Proceedings of the USENIX Workshop on Accurate Electronic Voting Technology
Ballot casting assurance via voter-initiated poll station auditing
EVT'07 Proceedings of the USENIX Workshop on Accurate Electronic Voting Technology
Active hardware metering for intellectual property protection and security
SS'07 Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium
Finding the Evidence in Tamper-Evident Logs
SADFE '08 Proceedings of the 2008 Third International Workshop on Systematic Approaches to Digital Forensic Engineering
A Prototype of Trusted Platform Functionality on Reconfigurable Hardware for Bitstream Updates
RSP '08 Proceedings of the 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping
Parametric, Secure and Compact Implementation of RSA on FPGA
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
VoteBox: a tamper-evident, verifiable electronic voting system
SS'08 Proceedings of the 17th conference on Security symposium
Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Coercion Resistant End-to-end Voting
Financial Cryptography and Data Security
On voting machine design for verification and testability
Proceedings of the 16th ACM conference on Computer and communications security
FORTUNA-A framework for the design and development of hardware-based secure systems
Journal of Systems and Software
| Hi-index | 0.00 |
This paper describes a minimal implementation of a cryptographically secure electronic voting system, built with a low-cost Xilinx FPGA board. This system, called VoteBox Nano, follows the same basic design principles as VoteBox, a full-featured electronic voting system. As with VoteBox, the votes are encrypted using Elgamal homomorphic encryption and the accuracy of the system can be challenged by real voters during an ongoing election. In order to fit within the limits of a minimal FPGA, VoteBox Nano eliminates VoteBox's sophisticated network replication and storage facilities. In return, VoteBox Nano runs without any operating systems or language runtime system, radically shrinking the implementation complexity. VoteBox Nano also integrates a hardware true random number generator, providing improved security for the ballot cryptography. In order to deter hardware tampering, which might be done to compromise the random number generator, the FPGA's native JTAG interface can be used to verify the FPGA's configuration. At boot-time, the proper FPGA configuration also displays a random number on the built-in display. Any interaction with the JTAG interface will replace the random number with another one, allowing poll workers to detect election-day tampering, simply by observing whether the number has changed.