Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A dynamically reconfigurable communication architecture for multicore embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
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Dynamic reconfiguration for fine-grained architectures is still associated with significant reconfiguration costs. In this paper, a new placement algorithm is proposed to reduce the size of FPGA reconfiguration bitstream. The algorithm is modified on the existing placement algorithm within VPR. It introduces the CLBs configuration of the previous circuit into cost function to increase similarity of CLBs configuration for subsequent circuits at the layout level. By using difference-based partial reconfiguration design flow, the proposed approach is validated by experiments on Xilinx Virtex FPGA platform, and experimental results show that the size of reconfiguration bitstream can be reduced.