Compile-time scheduling of dataflow program graphs with dynamic constructs
Compile-time scheduling of dataflow program graphs with dynamic constructs
Bounded scheduling of process networks
Bounded scheduling of process networks
Compile-Time Scheduling of Dynamic Constructs in Dataflow Program Graphs
IEEE Transactions on Computers
Software Synthesis from Dataflow Graphs
Software Synthesis from Dataflow Graphs
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Reconfigurable architectures for general-purpose computing
Reconfigurable architectures for general-purpose computing
Network-flow-based multiway partitioning with area and pin constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Run-time support for dynamically reconfigurable computing systems
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
Efficiently scheduling runtime reconfigurations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Static run-time mode extraction by state partitioning in synchronous process networks
Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems
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The SCORE compute model uses fixed-size, virtual compute and memory pages connected by stream links to capture the definition of a computation abstracted from the detailed size of the physical hardware. When the number of physical compute pages is smaller than the number of virtual compute pages in the abstract computation graph, the design is time-multiplexed onto the available physical hardware. A key component of this strategy is an automatic scheduler that selects the temporal sequencing of virtual resources onto the physical device. We describe a quasi-static scheduling strategy that retains the full semantic power of the dynamic SCORE flow graph while taking advantage of static scheduling techniques at program load time to hoist most of the computational work out of the inner scheduling loops. This strategy reduces online scheduling work per reconfiguration epoch by an order of magnitude. In addition, a more global perspective available from offline-scheduling improves schedule quality, resulting in a net reduction of total execution time by 46--81%.