Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Poly-DWT: Polymorphic wavelet hardware support for dynamic image compression
ACM Transactions on Embedded Computing Systems (TECS)
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This paper presents an FPGA architecture for the separable 2-D Biorthogonal Discrete Wavelet Transform (DWT) decomposition. The architecture is based on the Pyramid Algorithm Analysis, which handles computation along the border efficiently by using the method of symmetric extension. For a J stage wavelet transform of NxN images, our architecture has a period of N虏 cycles per NxN image, and requires only the minimum intermediate storage size necessary. The architecture is highly scalable for different filter lengths and different octave levels. The design of a specific 2-D Biorthogonal 9&7 Wavelet Transform and its implementation on the Xilinx Virtex-E is taken as a case study.