A Parallel Architecture for the 2-D Discrete Wavelet Transform with Integer Lifting Scheme
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
An efficient architecture for lifting-based two-dimensional discrete wavelet transforms
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IEEE Transactions on Circuits and Systems for Video Technology
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IEEE Transactions on Circuits and Systems for Video Technology
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ICANNGA '07 Proceedings of the 8th international conference on Adaptive and Natural Computing Algorithms, Part II
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FPGA implementation of multiplierless 5/3 LeGall discrete wavelet transform using lifting approach
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Proceedings of the International Conference on Advances in Computing, Communications and Informatics
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An architecture for the lifting-based two-dimensional discrete wavelet transform is presented. The architecture has regular data flow and low control complexity, and achieves 100% hardware utilization. It is easily adapted to arbitrary image sizes, multiple levels of transform, and different numbers of lifting steps. Symmetric extension of the image to be transformed is handled in a way that does not require additional computations or clock cycles. The proposed architecture achieves higher throughput and uses 30% fewer lines of embedded memory than architectures based on convolutional filter banks. The architecture has been implemented on an Altera APEX20KE field programmable gate array for three differently quantized versions of the biorthogonal 9/7 filter set used for JPEG2000 lossy compression. Our best implementation of a one-level two-dimensional discrete wavelet transform achieves a throughput of 66.8 megapixels per second using 7726 logic elements.