The lifting scheme: a construction of second generation wavelets
SIAM Journal on Mathematical Analysis
An efficient architecture for lifting-based two-dimensional discrete wavelet transforms
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
A VLSI architecture for lifting-based forward and inverse wavelettransform
IEEE Transactions on Signal Processing
Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000
IEEE Transactions on Circuits and Systems for Video Technology
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In this paper, we propose a deeply parallel architecture called Fragment-based Interleaving Dual Pipelines(FIDP) which can exploit all parallelisms in Lifting-based 2D DWT algorithm. FIDP adopts a fragment-based samples consumption policy and consists of two row processors and two column processors. These processors are organized as interleaving dual pipelines to operate effectively. FIDP takes N2/4+N/2+1 cycles to finish a N×N 2D DWT while requires only 5N+2 buffer.