A Parallel Architecture for the 2-D Discrete Wavelet Transform with Integer Lifting Scheme

  • Authors:
  • M. Ferretti;D. Rizzo

  • Affiliations:
  • DIS, University of Pavia, Via Ferrata 1, 27100 Pavia, Italy;DIS, University of Pavia, Via Ferrata 1, 27100 Pavia, Italy

  • Venue:
  • Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
  • Year:
  • 2001

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Abstract

In this paper we propose a dedicated architecture to implement a 2-D discrete wavelet transform computed by adopting the new lifting scheme framework. Through this new construction tool it is possible to obtain integer versions of the wavelet transform. This is a very interesting issue when the goal is lossless compression of images, whose pixels are represented through integers. In the classical approach to the discrete wavelet, the filter coefficients are real numbers and so are the resulting coefficients. When pursuing hardware implementations for real time and embedded applications, this causes the need to manage fixed point operations and unavoidable quantization. If the output can be produced with integer values instead, perfect reconstruction and lossless compression are possible. Typical applications include scenarios with limited bandwidth and big image sizes, such as medical imaging for tele-medicine or satellite image transmission, not suited to lossy compression, or high quality images in digital cameras.We analyze the data flow and dependencies to define an architecture to implement the integer lifting wavelet transform. The paper covers all lifting implementations based on a single ‘lifting stepr’ and uses the Deslauriers-Dubuc (4, 2) filter as a guiding example, but the approach is general and the results can be easily extended to other filters. We outline a very general framework, to be used either in a custom VLSI implementation, or in mappings onto existing ‘computing cells’. The overall resources needed are less than those for the equivalent classical FIR version computed through a systolic architecture.