A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000

  • Authors:

  • G. Dimitroulakos;M. D. Galanis;A. Milidonis;C. E. Goutis

  • Affiliations:

  • VLSI Design Laboratory, Electrical and Computer Engineering Department, University of Patras, Patras, Greece;VLSI Design Laboratory, Electrical and Computer Engineering Department, University of Patras, Patras, Greece;VLSI Design Laboratory, Electrical and Computer Engineering Department, University of Patras, Patras, Greece;VLSI Design Laboratory, Electrical and Computer Engineering Department, University of Patras, Patras, Greece

  • Venue:
  • Integration, the VLSI Journal
  • Year:
  • 2005

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Abstract

In this paper, the design and implementation of an optimized hardware architecture in terms of speed and memory requirements for computing the tile-based 2D forward discrete wavelet transform for the JPEG2000 image compression standard, are described. The proposed architecture is based on a well-known architecture template for calculating the 2D forward discrete wavelet transform. This architecture is derived by replacing the filtering units by our previously published throughput-optimized ones and by developing a scheduling algorithm suited to the special features of our filtering units. The architecture exhibits high-performance characteristics due to the throughput-optimized filters. Also, the extra clock cycles required due to the tile-based version of the discrete wavelet transform are partially compensated by the proper scheduling of the filters. The developed scheduling algorithm results in reduced memory requirements compared with existing architectures.