Ten lectures on wavelets
VLSI implementation of discrete wavelet transform
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A motion compensated lifting wavelet codec for 3D video coding
Journal of Computer Science and Technology
IEEE Transactions on Signal Processing
A VLSI architecture for lifting-based forward and inverse wavelettransform
IEEE Transactions on Signal Processing
IEEE Transactions on Signal Processing
Line-based, reduced memory, wavelet image compression
IEEE Transactions on Image Processing
Combined line-based architecture for the 5-3 and 9-7 wavelet transform of JPEG2000
IEEE Transactions on Circuits and Systems for Video Technology
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In this paper, we propose a VLSI architecture that performs the line-based discrete wavelet transform (DWT) using a lifting scheme. The architecture consists of row processors, column processors, an intermediate buffer and a control module. Row processor and Column processor work as the horizontal and vertical filters respectively. Intermediate buffer is composed of five FIFOs to store temporary results of horizontal filter. Control module schedules the output order to external memory. Compared with existing ones, the presented architecture parallelizes all levels of wavelet transform to compute multilevel DWT within one image transmission time, and uses no external but one intermediate buffer to store several line results of horizontal filtering, which decreases resource required significantly and reduces memory efficiently. This architecture is suitable for various real-time image/video applications.