Algorithms for scalable synchronization on shared-memory multiprocessors
ACM Transactions on Computer Systems (TOCS)
Cache-based synchronization in shared memory multiprocessors
Journal of Parallel and Distributed Computing
Efficient synchronization: let them eat QOLB
Proceedings of the 24th annual international symposium on Computer architecture
UNIX network programming, volume 2 (2nd ed.): interprocess communications
UNIX network programming, volume 2 (2nd ed.): interprocess communications
System-on-a-chip processor synchronization support in hardware
Proceedings of the conference on Design, automation and test in Europe
The Performance of Spin Lock Alternatives for Shared-Memory Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Efficient Software Synchronization on Large Cache Coherent Multiprocessors
Efficient Software Synchronization on Large Cache Coherent Multiprocessors
Hardware/software co-design of run-time systems
Hardware/software co-design of run-time systems
Mechanisms for efficient shared-memory, lock-based synchronization
Mechanisms for efficient shared-memory, lock-based synchronization
A Hardware-Software Real-Time Operating System Framework for SoCs
IEEE Design & Test
Hardware Support for Priority Inheritance
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Hardware/Software Partitioning of Operating Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
PARLAK: Parametrized Lock Cache Generator
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A comparison of the RTU hardware RTOS with a hardware/software RTOS
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Distributed and low-power synchronization architecture for embedded multiprocessors
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
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Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory System-on-a-Chip implementation. These overheads are observed in terms of lock latency, lock delay and memory bandwidth consumption in the system. It has been shown that a hardware solution brings a much better performance improvement than the synchronization algorithms developed in software [3]. Our previous work presented a SoC Lock Cache (SoCLC) hardware mechanism which resolves the Critical Section (CS) interactions among multiple processors and improves the performance criteria in terms of lock latency, lock delay and bandwidth consumption in a shared memory multi-processor SoC for short CSes [1]. This paper extends our previous work to support long CSes as well. This combined support involves modifications both in the RTOS kernel level facilities (such as support for preemptive versus non-preemptive synchronization, interrupt handling and RTOS initialization) and in the hardware mechanism. The worst-case simulation results of a database application model with client-server pair of tasks on a four-processor system showed that our mechanism achieved a 57% improvement in lock latency, 14% speed up in lock delay and a 35% overall speedup in total execution time.