Stack-based scheduling for realtime processes
Real-Time Systems
Multiprocessor priority ceiling based protocols
Multiprocessor priority ceiling based protocols
Priority ceiling protocol in Ada
Proceedings of the conference on TRI-Ada '96: disciplined software development with Ada
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
System-on-a-chip processor synchronization support in hardware
Proceedings of the conference on Design, automation and test in Europe
A system-on-a-chip lock cache with task preemption support
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Priority Inheritance Protocols: An Approach to Real-Time Synchronization
IEEE Transactions on Computers
PARLAK: Parametrized Lock Cache Generator
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
International Journal of Information and Communication Technology
ICCS '07 Proceedings of the 7th international conference on Computational Science, Part IV: ICCS 2007
Parallel, hardware-supported interrupt handling in an event-triggered real-time operating system
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Implementing OS components in hardware using AOP
ACM SIGOPS Operating Systems Review
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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Previous work has shown that a system-on-a-chip lockcache (SoCLC) reduces on-chip memory traffic, providesa fair and fast lock hand-off, simplifies software, increasesthe real-time predictability of the system and improvesperformance. In this research work, we extendthe SoCLC mechanism with a priority inheritance supportimplemented in hardware. Priority inheritance providesa higher level of real-time guarantees for synchronizingapplication tasks. Experimental results indicate thatour SoCLC hardware mechanism with priority inheritanceachieves a 36% speedup in lock delay, 88% speedup in locklatency and 15% speedup in the overall execution time whencompared to its software counterpart. The cost in terms ofadditional hardware area for the SoCLC with priority inheritanceis approximately 10,000 NAND2 gates.