ICARUS: A Dynamically Reconfigurable Computer Architecture

Authors:
Michael Baxter
Affiliations:
-
Venue:
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
1999

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Abstract

ICARUS (Image Computing, Automatically Reconfigurable, Unlimited Scale), is an architecture for general purpose parallel computing. The current implementation uses standard FPGAs in novel ways, has no host CPU and differs in many ways from the fixed CPU plus variable FPGA" approach to computing. Different instruction set architectures (ISAs) are loaded automatically during runtime. Two key architectural elements are S-Machines (Symbolic Machines), and T-Machines (Transaction Machines).