Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core

Authors:
Didier Keymeulen;Adrian Stoica;Ricardo Zebulum;Srinivas Katkoori;Pradeep Fernando;Hariharan Sankaran;Mohammad Mojarradi;Taher Daud
Affiliations:
Jet Propulsion Laboratory, California Institute of Technology, Pasadena, USA 91109;Jet Propulsion Laboratory, California Institute of Technology, Pasadena, USA 91109;Jet Propulsion Laboratory, California Institute of Technology, Pasadena, USA 91109;University of South Florida, Tampa, USA FL 33620;University of South Florida, Tampa, USA FL 33620;University of South Florida, Tampa, USA FL 33620;Jet Propulsion Laboratory, California Institute of Technology, Pasadena, USA 91109;Jet Propulsion Laboratory, California Institute of Technology, Pasadena, USA 91109
Venue:
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
Year:
2008

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Abstract

Development of analog electronics solutions for space avionics is expensive and time-consuming. Lack of flexible analog devices, counterparts to digital Field Programmable Gate Arrays (FPGA), prevents analog designers from the benefits of rapid prototyping. This forces them to expensive and lengthy custom design, fabrication, and qualification of application specific integrated circuits (ASIC). This paper describes a recent FPAA design, the Self-Reconfigurable Analog Array (SRAA) that was developed at JPL. It has a large variety of analog building block components in the cells of the array and allows to operate over a wide range of temperature using a built in general purpose genetic algorithm (GA) engine as an intellectual property (IP) core.