Space or time adaptive signal processing by neural network models
AIP Conference Proceedings 151 on Neural Networks for Computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
A New Research Tool for Intrinsic Hardware Evolution
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
Analogue EHW Chip for Intermediate Frequency Filters
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
EH '02 Proceedings of the 2002 NASA/DoD Conference on Evolvable Hardware (EH'02)
Evolving Circuits in Seconds: Experiments with a Stand-Alone Board-Level Evolvable System
EH '02 Proceedings of the 2002 NASA/DoD Conference on Evolvable Hardware (EH'02)
Progress And Challenges In Building Evolvable Devices
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
Pama - Programmable Analog Multiplexer Array
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
Speed enhancement with soft computing hardware
ICANN/ICONIP'03 Proceedings of the 2003 joint international conference on Artificial neural networks and neural information processing
Transistor-level circuit experiments using evolvable hardware
IWINAC'05 Proceedings of the First international work-conference on the Interplay Between Natural and Artificial Computation conference on Artificial Intelligence and Knowledge Engineering Applications: a bioinspired approach - Volume Part II
Hi-index | 0.00 |
In this paper we describe the hardware evolution of analog circuits performing signal separation tasks using JPL's Stand-Alone Board-Level Evolvable System (SABLES). SABLES integrates a Field Programmable Transistor Array chip (FPTA-2) and a Digital Signal Processor (DSP) implementing the Evolutionary Platform (EP). The FPTA-2 is a second generation reconfigurable mixed signal array chip whose cells can be programmed at the transistor level. Its chip architecture consists of an 8×8 matrix of reconfigurable cells. The FPTA-2 is reconfigured by evolution to achieve circuits that can extract a target signal that is combined with an undesired component or to perform the separation of a combination of two signals. The paper considers also an adaptive filter where the fitness function depends on the input signal. The results demonstrate that SABLES is not only able to perform signal separation and extraction, but it is also flexible enough to adapt to different input signals without human intervention, such as in the case of self-tuning and adaptive filters.