Massively Parallel Hardware Architecture for Genetic Algorithms

Authors:
Nadia Nedjah;Luiza de Macedo Mourelle
Affiliations:
State University of Rio de Janeiro;State University of Rio de Janeiro
Venue:
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
Year:
2005

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Abstract

As feature sizes continue to decrease and clock rates and device count on a VLSI chip increase, it becomes increasingly more difficult to maintain yields at their present levels. Process variation, noise and spot defects create very costly problems for ...