Fault-Tolerant Hierarchical Interconnection Networks Constructed by Additional Bypass Linking with Graph-Node Coloring

• Authors: Nobuo Tsuda
• Venue: DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
• Year: 1997

A hierarchical redundancy scheme using additional bypass linking (ABL) is proposed for constructing fault-tolerant massively parallel computers with hierarchically ring-connected, mesh-connected, and cube-connected interconnection networks. This scheme enables a redundant hierarchical network to be constructed with a simple nested structure by using a feature of the ABL scheme, which is that it uses graph-node coloring for bypass allocation to the component network in order to minimize the number of bypass links and that the redundant component network can be treated as a processing element (PE) with a fixed number of external connections if these connections are provided in the bypass links. The spare circuits with hierarchical structures can greatly enhance PE-to-PE communications while achieving strong fault tolerance.